Let’s first look at what happens when we run this trivial VHDL code in the ModelSim VHDL simulator:
To precisely model the behavior of digital logic, simulators use an event-based approach for executing VHDL code. While in VHDL, there can be multiple sequences of logic that react to each other in ways that are not compatible with the standard computer architecture. When a normal programming language is run, the CPU executes one instruction after the other. VHDL is a parallel programming language, while computers and CPUs work in a sequential manner. They are events that happen in zero simulation time after a preceding event. Delta cycles are non-time-consuming timesteps used by VHDL simulators for modeling events during execution of VHDL code.
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